The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 11, 2022

Filed:

Sep. 25, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Ju Youn Kim, Suwon-si, KR;

Sang Jung Kang, Suwon-si, KR;

Ji Su Kang, Seoul, KR;

Yun Sang Shin, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/12 (2006.01); H01L 29/49 (2006.01); H01L 27/092 (2006.01); H01L 21/8238 (2006.01); H01L 29/786 (2006.01); H01L 21/762 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0924 (2013.01); H01L 21/76224 (2013.01); H01L 21/823821 (2013.01); H01L 21/823878 (2013.01); H01L 29/0653 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01); H01L 29/7851 (2013.01); H01L 29/78696 (2013.01);
Abstract

A semiconductor device includes a substrate including NMOS and PMOS regions; first and second active patterns on the NMOS region; third and fourth active patterns on the PMOS region, the third active pattern being spaced apart from the first active pattern; a first dummy gate structure on the first and third active patterns; a second dummy gate structure on the second and fourth active patterns; a normal gate structure on the third active pattern; a first source/drain pattern on the third active pattern and between the normal gate structure and the first dummy gate structure; and a first element separation structure between the first and second dummy gate structures and separating the third and fourth active patterns, wherein the first dummy gate structure includes a first dummy insulation gate intersecting the third active pattern.


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