The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 11, 2022

Filed:

Mar. 11, 2020
Applicant:

Dell Products, Lp, Round Rock, TX (US);

Inventors:

Stuart A. Berke, Austin, TX (US);

Jordan Chin, Austin, TX (US);

Ralph H. Johnson, Round Rock, TX (US);

Shiguo Luo, Austin, TX (US);

Assignee:

Dell Products L.P., Round Rock, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/4076 (2006.01); G11C 11/4074 (2006.01); G11C 5/04 (2006.01); G11C 5/14 (2006.01); H02M 3/156 (2006.01); G06F 1/324 (2019.01); G06F 13/42 (2006.01); H03L 7/081 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4076 (2013.01); G06F 1/324 (2013.01); G06F 13/4291 (2013.01); G11C 5/04 (2013.01); G11C 5/143 (2013.01); G11C 11/4074 (2013.01); H02M 3/156 (2013.01); H03L 7/0814 (2013.01); G06F 2213/0016 (2013.01);
Abstract

An memory subsystem of an information handling system includes a memory module and a controller. The memory module includes a Registering Clock Driver (RCD) configured to receive a clock signal. The RCD includes a delay setting and a clock delay circuit to provide a selectable delayed clock signal based upon the delay setting. The memory module further includes a power management integrated circuit (PMIC) with a plurality of switching regulators. The PMIC receives the delayed clock signal and clocks the switching regulators based upon the delayed clock signal. The controller sets the first delay setting.


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