The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 11, 2022

Filed:

Jul. 02, 2020
Applicant:

Google Llc, Mountain View, CA (US);

Inventors:

Yuanzhong Xu, Mountain View, CA (US);

James M. Stichnoth, San Jose, CA (US);

David Alexander Majnemer, Mountain View, CA (US);

Assignee:

Google LLC, Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/38 (2018.01); G06F 9/30 (2018.01); G06F 9/46 (2006.01); G06F 9/44 (2018.01); G06F 9/00 (2006.01); G06F 9/302 (2018.01); G06F 9/48 (2006.01);
U.S. Cl.
CPC ...
G06F 9/4881 (2013.01); G06F 9/3814 (2013.01); G06F 9/3855 (2013.01); G06F 9/3877 (2013.01);
Abstract

Methods, systems, and apparatus for scheduling first-in-first-out instructions are described. In one aspect, a method includes receiving data representing code of a program to be executed by a processing unit comprising hardware processors. For each of one or more of the hardware processors, an order of independent groups of first-in-first-out (FIFO) instructions for execution by the hardware processor is identified in the data representing the code of the program. For each independent group of FIFO instructions for execution by the hardware processor, a path length metric that represents how long it will take to reach an end of the program from the independent group of FIFO instructions is determined. A new order of the independent groups of FIFO instructions for execution by the hardware processor is generated based at least on the path length metric for each independent group of FIFO instructions for execution by the hardware processor.


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