The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 11, 2022

Filed:

Nov. 15, 2019
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Sho Yamanaka, Tokyo, JP;

Nobuhiko Honda, Tokyo, JP;

Takahiro Irita, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 11/10 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0653 (2013.01); G06F 3/0602 (2013.01); G06F 3/064 (2013.01); G06F 3/0619 (2013.01); G06F 3/0659 (2013.01); G06F 3/0671 (2013.01); G06F 11/1048 (2013.01);
Abstract

When a plurality of write data is merged to generate a code for protecting data stored in the main memory, the write data is protected in the memory controller. A first code generation unit generates a first code based on the write data stored in a first sub memory, and stores the generated first code in a second sub memory. The sub memory controller reads the write data to be merged from the first sub memory, and verifies whether the read write data includes an error by using the first code stored in the second sub memory. When the read write data does not include an error, the sub memory controller merges valid data of the write data read from the first sub memory, and outputs the merged data to a second code generation unit. The second code generation unit generates a second code based on the merged data.


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