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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11221606 B1

PDFFull Text
Date of Patent:
Jan. 11, 2022

Filed:

Jul. 25, 2018

System and method for depicting and using one logical connection with collection of input/output (i/o) modules as multiple individual logical connections

Applicant:

Honeywell International Inc., Morris Plains, NJ (US);

Inventors:

Suraj Prakash, Ranchi, IN;

Sameer Gupta, Lucknow, IN;

Laxmana Rao Paruchuri, Kollipara, IN;

Assignee:

Honeywell International Inc., Morris Plains, NJ (US);

Attorneys:

Paschall & Associates. LLC

James C. Paschall

Primary Examiner:

Henry Tsai

Assistant Examiner:

Christopher A Bartels

Int. Cl.
CPC ...
G05B 19/042 (2006.01); G05B 19/05 (2006.01); G06F 8/65 (2018.01); G06F 9/451 (2018.01); G06F 3/0484 (2013.01); G06F 9/445 (2018.01); G06F 8/654 (2018.01);
U.S. Cl.
CPC ...
G05B 19/0423 (2013.01); G05B 19/05 (2013.01); G06F 3/04842 (2013.01); G06F 8/65 (2013.01); G06F 9/44505 (2013.01); G06F 9/453 (2018.02); G06F 8/654 (2018.02); G06F 9/451 (2018.02);
Abstract

A method includes presenting a graphical user interface to a user, where the graphical user interface identifies multiple slots that are configured to be coupled to multiple input/output (I/O) modules. The method also includes receiving, from the user via the graphical user interface, information defining a slot assembly data map. The slot assembly data map identifies data offsets and data sizes associated with the I/O modules. The data offsets and the data sizes identify where data can be sent to or received from the multiple I/O modules over a single logical connection. The method further includes using the data offsets and the data sizes of the slot assembly data map to provide data to or receive data from one or more of the I/O modules over the single logical connection.

Find Patent Forward Citations

Prakash, Suraj. (2022). System and method for depicting and using one logical connection with collection of input/output (i/o) modules as multiple individual logical connections (U.S. Patent No. 11221606). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11221606

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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