The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 11, 2022

Filed:

Jun. 07, 2019
Applicant:

Samsung Display Co., Ltd., Yongin-Si, KR;

Inventors:

Ki Pyo Hong, Hwaseong-si, KR;

Wan Namgung, Asan-si, KR;

Seung-Kyu Lee, Cheonan-si, KR;

Hyun Seong Kang, Cheonan-si, KR;

Byeong Jae Ahn, Asan-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/1368 (2006.01); G02F 1/1343 (2006.01); G02F 1/01 (2006.01); G02F 1/1362 (2006.01); G02F 1/133 (2006.01);
U.S. Cl.
CPC ...
G02F 1/1343 (2013.01); G02F 1/0123 (2013.01); G02F 1/13306 (2013.01); G02F 1/136286 (2013.01);
Abstract

A liquid crystal display includes: a gate line connected to a gate electrode; a semiconductor layer disposed on the gate line and including silicon; an ohmic contact layer disposed on the semiconductor layer; and a data conductor disposed on the ohmic contact layer. The semiconductor layer includes a source region, a drain region, and a channel region disposed between the source region and the drain region. The data conductor includes a data line transmitting a data signal, a source electrode corresponding to the source region, and a drain electrode corresponding to the drain region. A channel step of the semiconductor layer is a height difference between an upper surface in the source region or the drain region and an upper surface in the channel region. The upper surface in the source region or the drain region has a maximum height of the semiconductor layer.


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