The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 11, 2022

Filed:

Feb. 05, 2020
Applicant:

General Electric Company, Schenectady, NY (US);

Inventor:

Sudeep Pathak, Hyderabad, IN;

Assignee:

General Electric Company, Schenectady, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/54 (2020.01); H02J 13/00 (2006.01); G05B 19/04 (2006.01); G05B 19/042 (2006.01); G01R 31/327 (2006.01); H02J 3/00 (2006.01);
U.S. Cl.
CPC ...
G01R 31/54 (2020.01); G01R 31/3278 (2013.01); G05B 19/0428 (2013.01); H02J 3/001 (2020.01); H02J 13/00002 (2020.01); H02J 13/00036 (2020.01); G05B 2219/31356 (2013.01);
Abstract

Power systems are disclosed. The power system may include at least one computing device in communication with a control circuit including a plurality of electrical loops. The computing device(s) may be configured to test each of the plurality of electrical loops of the control circuit by performing processes including configuring a first electrical loop in a first electrical setting by adjusting an operational characteristic of one or more electrical switch(s) of the first electrical loop. The processes may also include determining an actual electrical status of the first electrical loop in the first electrical setting based on whether a relay of a return line in the first electrical loop detects a supplied voltage. Additionally, the computing device(s) may detect a fault in the first electrical loop in response to the determined actual electrical status of the first electrical loop differing from an expected electrical status of the first electrical loop.


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