The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 04, 2022

Filed:

Apr. 15, 2020
Applicant:

Silicon Motion, Inc., Jhubei, TW;

Inventor:

Shiuan-Hao Kuo, New Taipei, TW;

Assignee:

SILICON MOTION, INC., Jhubei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/11 (2006.01); H03M 13/31 (2006.01); H03M 13/09 (2006.01); H03M 13/17 (2006.01);
U.S. Cl.
CPC ...
H03M 13/1157 (2013.01); H03M 13/09 (2013.01); H03M 13/1105 (2013.01); H03M 13/1142 (2013.01); H03M 13/1177 (2013.01); H03M 13/17 (2013.01); H03M 13/31 (2013.01);
Abstract

A method for generating an LDPC (low-density parity check) code with a required error floor, comprising: using a parity generation circuit to generate an LDPC code; using a detection circuit to detect the LDPC code according to a plurality of trapping set cores in a database and to generate at least one piece of trapping-set-core information; using a verification circuit to perform an important sampling simulation according to the LDPC code and each trapping-set-core information separately to obtain an estimated error floor for each trapping-set-core information; using the verification circuit to separately compare each of the estimated error floors with an expected error floor; and when all of the estimated error floors are lower than or equal to the expected error floor, using the verification circuit to output the LDPC code.


Find Patent Forward Citations

Loading…