The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 04, 2022
Filed:
Sep. 12, 2019
Applicant:
Siliconix Incorporated, San Jose, CA (US);
Inventors:
Sanjay Havanur, San Jose, CA (US);
M. Ayman Shibib, San Jose, CA (US);
Assignee:
Vishay-Siliconix, LLC, San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 17/0812 (2006.01); H03K 17/567 (2006.01); H01L 27/07 (2006.01); H01L 29/423 (2006.01); H01L 29/778 (2006.01); H01L 29/866 (2006.01); H01L 29/78 (2006.01); H01L 29/20 (2006.01);
U.S. Cl.
CPC ...
H03K 17/08122 (2013.01); H01L 27/0727 (2013.01); H01L 29/2003 (2013.01); H01L 29/4236 (2013.01); H01L 29/7787 (2013.01); H01L 29/7808 (2013.01); H01L 29/7813 (2013.01); H01L 29/866 (2013.01); H03K 17/567 (2013.01);
Abstract
Semiconductor device with multiple independent gates. A gate-controlled semiconductor device includes a first plurality of cells of the semiconductor device configured to be controlled by a primary gate, and a second plurality of cells of the semiconductor device configured to be controlled by an auxiliary gate. The primary gate is electrically isolated from the auxiliary gate, and sources and drains of the semiconductor device are electrically coupled in parallel. The first and second pluralities of cells may be substantially identical in structure.