The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 04, 2022
Filed:
May. 14, 2020
Clint Wayne Mumford, Apex, NC (US);
Kshitiz Saxena, Cary, NC (US);
Miguel Comparan, Kenmore, WA (US);
Adam Muff, Woodingville, WA (US);
Oscar Rosell, Hospitalet de Llobregat, ES;
Clint Wayne Mumford, Apex, NC (US);
Kshitiz Saxena, Cary, NC (US);
Miguel Comparan, Kenmore, WA (US);
Adam Muff, Woodingville, WA (US);
Oscar Rosell, Hospitalet de Llobregat, ES;
NORTHROP GRUMMAN SYSTEMS CORPORATION, Falls Church, VA (US);
Abstract
Ring packet built-in self-test (PBIST) circuitry configured to detect errors in wires connecting a ring of superconducting chips includes circuitry configured to make the PBIST immune to interchip latency and still allow the PBIST to test a stop-to-stop connection. By making a PBIST independent of latency, an entire ring can be characterized for latency and for its bit-error rate prior to running any functional test. Such systems and associated methods can be scaled to larger platforms having any number of ring stops. The PBIST circuitry can function as either transmitter or receiver, or both, to test an entire ring. The PBIST can also be used to tune clocks in the ring to achieve the lowest overall bit error rate (BER) in the ring.