The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 04, 2022
Filed:
Mar. 18, 2020
Applicant:
Analog Devices, Inc., Norwood, MA (US);
Inventors:
Ed Balboni, Littleton, MA (US);
Ozan Gurbuz, Portland, OR (US);
Assignee:
ANALOG DEVICES, INC., Wilmington, MA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01Q 1/22 (2006.01); H01L 23/522 (2006.01); H01L 23/66 (2006.01); H01L 23/528 (2006.01); H01L 21/306 (2006.01); H01L 21/288 (2006.01); H01Q 9/16 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01Q 1/2283 (2013.01); H01L 21/288 (2013.01); H01L 21/30604 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/66 (2013.01); H01L 23/53223 (2013.01); H01L 23/53238 (2013.01); H01L 23/53266 (2013.01); H01L 2223/6616 (2013.01); H01L 2223/6677 (2013.01); H01Q 9/16 (2013.01);
Abstract
One embodiment is an apparatus comprising a silicon-on-insulator ('SOI') substrate comprising an insulating layer sandwiched in between a bottom silicon layer and a top silicon layer; a radiating element disposed on a top surface of the SOI substrate; and at least one cavity disposed in the SOI substrate surrounding the radiating element, wherein the at least one cavity extends from a bottom surface of the bottom silicon layer to a bottom surface of the insulating layer.