The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 04, 2022

Filed:

Sep. 21, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Richard H. Boivie, Monroe, CT (US);

Eduard A. Cartier, New York, NY (US);

Daniel J. Friedman, Sleepy Hollow, NY (US);

Kohji Hosokawa, Kawasaki, JP;

Charanjit Jutla, New York, NY (US);

Wanki Kim, Chappaqua, NY (US);

Chandrasekara Kothandaraman, New York, NY (US);

Chung Lam, Peekskill, NY (US);

Frank R. Libsch, White Plains, NY (US);

Seiji Munetoh, Tokyo, JP;

Ramachandran Muralidhar, Mahopac, NY (US);

Vijay Narayanan, New York, NY (US);

Dirk Pfeiffer, Croton on Hudson, NY (US);

Devendra K. Sadana, Pleasantville, NY (US);

Ghavam G. Shahidi, Pound Ridge, NY (US);

Robert L. Wisnieff, Ridgefield, CT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 21/72 (2013.01); G06F 21/75 (2013.01); G11C 16/00 (2006.01);
U.S. Cl.
CPC ...
G06F 21/72 (2013.01); G06F 21/75 (2013.01); G11C 16/00 (2013.01);
Abstract

A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.


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