The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 04, 2022

Filed:

Nov. 14, 2019
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventor:

Won-Gyu Shin, Seoul, KR;

Assignee:

SK hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/10 (2006.01); H03M 13/09 (2006.01); G06F 12/02 (2006.01); H03M 13/15 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1064 (2013.01); G06F 11/102 (2013.01); G06F 11/1004 (2013.01); G06F 12/0246 (2013.01); H03M 13/09 (2013.01); H03M 13/1515 (2013.01); G06F 2212/7201 (2013.01);
Abstract

A memory system includes: a first error detection circuit suitable for generating a first error detection code using host data and a host address which are transferred from a host; a second error detection circuit suitable for generating a second error detection code using system data including one or more host data, a logical address corresponding to one or more host addresses, a physical address corresponding to the logical address and one or more first error detection codes; a third error detection code suitable for generating a third error detection code using the system data, the one or more first error detection codes and the second error detection code; and a first memory suitable for storing the system data, the one or more first error detection codes, the second error detection code and the third error detection code.


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