The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 04, 2022

Filed:

May. 21, 2020
Applicant:

Sharp Kabushiki Kaisha, Sakai, JP;

Inventors:

Hideki Kitagawa, Sakai, JP;

Yoshihito Hara, Sakai, JP;

Masaki Maeda, Sakai, JP;

Yoshiharu Hirata, Sakai, JP;

Tatsuya Kawasaki, Sakai, JP;

Teruyuki Ueda, Sakai, JP;

Hajime Imai, Sakai, JP;

Tohru Daitoh, Sakai, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
G02F 1/136286 (2013.01); G02F 1/1368 (2013.01); H01L 27/124 (2013.01); H01L 27/1225 (2013.01); H01L 27/1248 (2013.01); H01L 27/1251 (2013.01); H01L 27/1288 (2013.01); G02F 2201/121 (2013.01); G02F 2201/123 (2013.01);
Abstract

An active matrix substrate includes: a substrate; lower bus lines and upper bus lines; a lower insulating layer positioned between the lower bus lines and the upper bus lines; an oxide semiconductor TFT that are disposed in each pixel region and have an oxide semiconductor layer disposed on the lower insulating layer; pixel electrodes disposed in each pixel region; and wiring connection units arranged in a non-display region. Each wiring connection unit includes: a lower conductive layer formed using the same conductive film as the lower bus lines; an insulating layer that extends on the lower conductive layer and includes the lower insulating layer. The lower bus lines and the lower conductive layer have a first laminated structure including a metal layer and a transparent conductive layer that covers an upper surface and a side surface of the metal layer.


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