The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 04, 2022

Filed:

Jul. 10, 2019
Applicant:

Facebook Technologies, Llc, Menlo Park, CA (US);

Inventors:

Ye Yin, Pleasanton, CA (US);

Rui Zhang, Sunnyvale, CA (US);

Assignee:

Facebook Technologies, LLC, Menlo Park, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); G09G 3/00 (2006.01); G01R 1/067 (2006.01); G02F 1/13 (2006.01); H01R 12/79 (2011.01); G01R 1/04 (2006.01);
U.S. Cl.
CPC ...
G01R 31/2825 (2013.01); G01R 1/0416 (2013.01); G01R 1/06722 (2013.01); G02F 1/1309 (2013.01); G09G 3/006 (2013.01); H01R 12/79 (2013.01); H01R 2201/20 (2013.01);
Abstract

The disclosed computer-implemented method may include providing test signals from a panel test board included in a fixture to a device under test included in a carrier including providing interface signals from the panel test board to a connector included on a fixture interposer block included in the fixture, interfacing the connector on the fixture interposer block with one or more pogo pins included on a panel interposer board included in the carrier, the interfacing providing the interface signals as inputs to a re-timer circuit included on the panel interposer board, generating, by the re-timer circuit, output interface signals whose signal strength is greater than a signal strength of the interface signals input to the re-timer circuit, and providing the interface signals output from the re-timer circuit to the device under test. Various other methods, systems, and computer-readable media are also disclosed.


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