The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 28, 2021

Filed:

Aug. 21, 2020
Applicant:

Kaneka Corporation, Osaka, JP;

Inventors:

Ryota Mishima, Osaka, JP;

Kunihiro Nakano, Osaka, JP;

Katsunori Konishi, Osaka, JP;

Daisuke Adachi, Osaka, JP;

Takashi Kuchiyama, Osaka, JP;

Kenji Yamamoto, Osaka, JP;

Assignee:

KANEKA CORPORATION, Osaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/20 (2006.01); H01L 31/0236 (2006.01); H01L 31/0747 (2012.01); H01L 31/18 (2006.01);
U.S. Cl.
CPC ...
H01L 31/202 (2013.01); H01L 31/02363 (2013.01); H01L 31/0747 (2013.01); H01L 31/1804 (2013.01);
Abstract

The method for manufacturing a solar cell includes: forming a first semiconductor layer of first conductivity type on a surface of a semiconductor substrate; forming a lift-off layer containing a silicon-based material on the first semiconductor layer; selectively removing the lift-off layer and first semiconductor layer; forming a second semiconductor layer of second conductivity type on a surface having the lift-off layer and first semiconductor layer; and removing the second semiconductor layer covering the lift-off layer by removing the lift-off layer using an etching solution. The linear expansion coefficients of the semiconductor substrate and the lift-off layer satisfy the relational expression: the linear expansion coefficient of the lift-off layer <the linear expansion coefficient of the semiconductor substrate, and the forming of the second semiconductor layer or the removing of the second semiconductor layer is performed at a temperature higher than the temperature in the forming of the lift-off layer.


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