The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 28, 2021

Filed:

Aug. 06, 2020
Applicant:

Samsung Display Co., Ltd., Yongin-si, KR;

Inventors:

Tetsuhiro Tanaka, Hwaseong-si, KR;

Yeong-Gyu Kim, Seoul, KR;

Ki Seong Seo, Seoul, KR;

Seung Hyun Lee, Asan-si, KR;

Chang Ho Yi, Suwon-si, KR;

Assignee:

SAMSUNG DISPLAY CO., LTD., Yongin-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); G09G 3/32 (2016.01); H01L 27/32 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1225 (2013.01); G09G 3/32 (2013.01); H01L 27/1237 (2013.01); H01L 27/1248 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/06 (2013.01); G09G 2330/028 (2013.01); H01L 27/1255 (2013.01); H01L 27/3258 (2013.01);
Abstract

A display device includes a polycrystalline semiconductor including a channel, a first electrode, and a second electrode of a driving transistor, a first gate insulating layer, a gate electrode of a driving transistor, a first electrode of a boost capacitor, a second gate insulating layer, a first interlayer insulating layer, an oxide semiconductor including a channel, a first electrode, and a second electrode of a second transistor, a channel, a first electrode, and a second electrode of a third transistor, and a second electrode of a boost capacitor, a third gate insulating layer disposed on the oxide semiconductor, a gate electrode of the second transistor overlapping the channel of the second transistor, a gate electrode of the third transistor overlapping the channel of the third transistor, and a second interlayer insulating layer disposed on the gate electrode of the second transistor and the gate electrode of the third transistor.


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