The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 28, 2021

Filed:

Sep. 09, 2019
Applicant:

Imec Vzw, Leuven, BE;

Inventors:

Shairfe Muhammad Salahuddin, Leuven, BE;

Jan Van Houdt, Bekkevoort, BE;

Julien Ryckaert, Schaerbeek, BE;

Alessio Spessot, Heverlee, BE;

Assignee:

IMEC vzw, Leuven, BE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/22 (2006.01); H01L 27/1159 (2017.01); G11C 11/4096 (2006.01); H01L 27/108 (2006.01); H01L 27/11587 (2017.01); H01L 27/11592 (2017.01);
U.S. Cl.
CPC ...
H01L 27/1159 (2013.01); G11C 11/223 (2013.01); G11C 11/2273 (2013.01); G11C 11/2275 (2013.01); G11C 11/4096 (2013.01); H01L 27/10844 (2013.01); H01L 27/10897 (2013.01); H01L 27/11587 (2013.01); H01L 27/11592 (2013.01);
Abstract

The disclosed technology is generally directed to semiconductor integrated circuit devices and more particularly to a three-transistor random access memory (3T RAM) device, and a method of fabricating and operating the same. In one aspect, a 3T RAM cell includes a ferroelectric-based field effect transistor (FeFET) having a first gate connected as a storage node and a second transistor connected between the FeFET and a read bit line having a second gate connected to a read word line. The 3T RAM cell also includes a third transistor connected between the storage node and a write bit line having a third gate connected to a write word line.


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