The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 28, 2021

Filed:

Jun. 30, 2020
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Sarath Puthenthermadam, San Jose, CA (US);

Yanli Zhang, San Jose, CA (US);

Huai-yuan Tseng, San Ramon, CA (US);

Peng Zhang, San Jose, CA (US);

Assignee:

SanDisk Technologies LLC, Addison, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11556 (2017.01); H01L 27/11582 (2017.01); H01L 29/06 (2006.01); G11C 5/06 (2006.01); G11C 5/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11556 (2013.01); G11C 5/025 (2013.01); G11C 5/06 (2013.01); H01L 27/11582 (2013.01); H01L 29/0638 (2013.01);
Abstract

A memory device disclosed herein. The memory device comprises: a memory string including a first select transistor, a memory cell transistor, and a second select transistor connected in series; a bit line connected to one end of the first select transistor; a source line connected to one end of the second select transistor; a first select line connected to a gate of the first select transistor; a word line connected to a gate of the memory cell transistor; a second select line connected to a gate of the second select transistor; and a control circuit configured to perform, before a program operation, a pre-charge operation comprising: applying a voltage to the second select line connected to the gate of the second select transistor to cause gate-induced drain leakage from the second select transistor.


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