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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11211349 B1

PDFFull Text
Date of Patent:
Dec. 28, 2021

Filed:

Jun. 24, 2020

Semiconductor device including a plurality of bonding pads

Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Seiya Isozaki, Tokyo, JP;

Tatsuya Kobayashi, Tokyo, JP;

Kota Jinno, Tokyo, JP;

Assignee:

RENESAS ELECTRONICS CORPORATION, Tokyo, JP;

Attorney:

McDermott Will & Emery LLP

Primary Examiner:

Mamadou L Diallo

Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/66 (2006.01); H01L 23/31 (2006.01); H01L 23/495 (2006.01); H01L 21/48 (2006.01); H01L 21/78 (2006.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H01L 24/05 (2013.01); H01L 21/4825 (2013.01); H01L 21/565 (2013.01); H01L 21/78 (2013.01); H01L 22/32 (2013.01); H01L 23/3114 (2013.01); H01L 23/4952 (2013.01); H01L 23/49513 (2013.01); H01L 24/48 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/05009 (2013.01); H01L 2224/48465 (2013.01); H01L 2924/351 (2013.01);
Abstract

A semiconductor device comprising: bonding pads formed in the first wiring layer; and first wirings and a second wiring formed in a second wiring layer provided one layer below the first wiring layer. Here, a power supply potential and a reference potential are to be supplied to each first wiring and the second wiring, respectively. Also, in transparent plan view, each of the first wirings is arranged next to each other, and is arranged at a first position of the second wiring layer, that is overlapped with the bonding region of the first bonding pad. Also, in transparent plan view, the second wiring is arranged at a second position of the second wiring layer, that is overlapped with a first region located between the first bonding pad and the second bonding pad. Further, a width of each first wiring is less than a width of the second wiring.

Find Patent Forward Citations

Isozaki, Seiya. (2021). Semiconductor device including a plurality of bonding pads (U.S. Patent No. 11211349). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11211349

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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