The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 28, 2021

Filed:

Jan. 22, 2020
Applicant:

Vanguard International Semiconductor Corporation, Hsinchu, TW;

Inventors:

Yung-Fong Lin, Taoyuan, TW;

Li-Wen Chuang, Taoyuan, TW;

Jui-Hung Yu, Tainan, TW;

Cheng-Tao Chou, Huwei Township, TW;

Chun-Hsu Chen, Sinpu Township, TW;

Yu-Chieh Chou, New Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/535 (2006.01); H01L 21/74 (2006.01); H01L 21/308 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 23/535 (2013.01); H01L 21/3081 (2013.01); H01L 21/31144 (2013.01); H01L 21/743 (2013.01); H01L 21/76804 (2013.01);
Abstract

A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure includes a substrate and a seed layer on the substrate. The substrate includes a base and a composite layer encapsulating the base. The semiconductor structure also includes an epitaxial layer on the seed layer. The semiconductor structure also includes a semiconductor device on the epitaxial layer, and an interlayer dielectric layer on the epitaxial layer. The interlayer dielectric layer covers the semiconductor device. The semiconductor structure further includes a via structure that penetrates at least the composite layer of the substrate and is in contact with the base.


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