The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 28, 2021

Filed:

May. 05, 2020
Applicant:

Ecole Polytechnique Federale DE Lausanne (Epfl), Lausanne, CH;

Inventors:

Marco Antonio Rios, Chavannes-Renens, CH;

William Andrew Simon, Prilly, CH;

Alexandre Sébastien Levisse, Lausanne, CH;

Marina Zapater, Chavannes-Renens, CH;

David Atienza Alonso, Echandens-Denges, CH;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01); G11C 11/419 (2006.01); G11C 11/418 (2006.01); G06F 7/523 (2006.01);
U.S. Cl.
CPC ...
G11C 11/419 (2013.01); G11C 7/1006 (2013.01); G11C 11/418 (2013.01); G06F 7/523 (2013.01);
Abstract

A random access memory array including a plurality of local memory group ways, each local memory group way including, a plurality of local memory groups, each local memory group including, a memory column including a plurality of memory cells, a pair of local bitlines operatively connected to the plurality of memory cells, and a local group periphery including a local bitline multiplexer operatively connected with the pairs of local bitlines of the corresponding local memory group; and a pair of global read bitlines operatively connected to outputs of the plurality of local group peripheries, a global read bitline multiplexer operatively connected to outputs of the plurality of pairs of the global read bitlines from the local memory group ways, and a bitline operational block operatively connected an output of the global read bitline multiplexer.


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