The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 28, 2021

Filed:

Jun. 04, 2019
Applicant:

Hannstar Display Corporation, Taipei, TW;

Inventors:

Chia-Hua Yu, New Taipei, TW;

Sung-Chun Lin, Tainan, TW;

Hsien-Tang Hu, Taichung, TW;

Hsuan-Chen Liu, Kaohsiung, TW;

Chien-Ting Chan, Tainan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/36 (2006.01); G02F 1/1362 (2006.01); H01L 27/12 (2006.01); G02F 1/1368 (2006.01); G02F 1/1345 (2006.01); G02F 1/136 (2006.01);
U.S. Cl.
CPC ...
G02F 1/136286 (2013.01); G02F 1/1368 (2013.01); H01L 27/1218 (2013.01); G02F 1/13454 (2013.01); G02F 1/13606 (2021.01); G02F 1/13629 (2021.01); G02F 2201/56 (2013.01); G09G 3/3677 (2013.01); G09G 2310/0286 (2013.01); G09G 2320/0233 (2013.01);
Abstract

A display panel has an odd-shaped active area and a peripheral area. The display panel includes a substrate, pixel units, gate lines and at least one dummy thin film transistor. The pixel units are disposed on the active area of the substrate. The gate lines are disposed on the substrate, each of the gate lines is coupled to one or more of the pixel units, and the number of pixel units coupled to a first gate line of the gate lines is smaller than the number of pixel units a second gate line coupled to of the gate lines. The dummy thin film transistor is disposed on the substrate, and is coupled to the first gate line.


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