The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 21, 2021
Filed:
Jan. 29, 2019
Battelle Memorial Institute, Richland, WA (US);
Seemita Pal, Richland, WA (US);
Arun Veeramany, Richland, WA (US);
Christopher A. Bonebrake, West Richland, WA (US);
Beverly E. Johnson, Richland, WA (US);
William James Hutton, III, Benton City, WA (US);
Siddharth Sridhar, Seattle, WA (US);
Sri Nikhil Gupta Gourisetti, Richland, WA (US);
Garill A. Coles, Richland, WA (US);
Battelle Memorial Institute, Richland, WA (US);
Abstract
Technology related to evaluating cyber-risk for synchrophasor systems is disclosed. In one example of the disclosed technology, a method includes generating an event tree model of a timing-attack on a synchrophasor system architecture. The event tree model can be based on locations and types of timing-attacks, an attack likelihood, vulnerabilities and detectability along a scenario path, and consequences of the timing-attack. A cyber-risk score of the synchrophasor system architecture can be determined using the event tree model. The synchrophasor system architecture can be adapted in response to the cyber-risk score.