The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 21, 2021

Filed:

Feb. 04, 2020
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Meysam Asadi, Fremont, CA (US);

Fan Zhang, Fremont, CA (US);

Aman Bhatia, Los Gatos, CA (US);

Xuanxuan Lu, San Jose, CA (US);

Haobo Wang, San Jose, CA (US);

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); H03M 13/11 (2006.01); H03M 13/00 (2006.01); G06F 11/10 (2006.01);
U.S. Cl.
CPC ...
H03M 13/1108 (2013.01); G06F 11/1068 (2013.01); H03M 13/116 (2013.01); H03M 13/6502 (2013.01);
Abstract

Devices, systems and methods for reducing complexity of a bit-flipping decoder for quasi-cyclic (QC) low-density parity-check (LDPC) codes are described. An example method includes receiving a noisy codeword that is based on a transmitted codeword generated from an irregular QC-LDPC code, the irregular QC-LDPC code having an associated parity matrix, storing, based on a weight of a plurality of columns of the parity matrix of the irregular QC-LDPC code, a portion of the noisy codeword corresponding to the plurality of columns in a first buffer of a plurality of buffers, and accessing and processing the portion of the noisy codeword that includes applying a vertically shuffled scheduling (VSS) scheme that uses a plurality of processing units to determine a candidate version of a portion of the transmitted codeword that corresponds to the portion of the noisy codeword.


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