The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 21, 2021

Filed:

Sep. 30, 2020
Applicant:

Chengdu Huawei Electronic Technology Co., Ltd., Chengdu, CN;

Inventors:

Qiang Yu, Chengdu, CN;

Yuanjun Cen, Chengdu, CN;

Jinda Yang, Chengdu, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/38 (2006.01); H03M 1/14 (2006.01); H03M 1/12 (2006.01); H03M 1/00 (2006.01); H03M 1/72 (2006.01); H02M 1/00 (2006.01); H03M 1/66 (2006.01);
U.S. Cl.
CPC ...
H03M 1/145 (2013.01); H02M 1/00 (2013.01); H03M 1/001 (2013.01); H03M 1/1205 (2013.01); H03M 1/662 (2013.01); H03M 1/72 (2013.01); H02M 1/0093 (2021.05);
Abstract

The disclosure belongs to the field of integrated circuits, and is used for reducing an area overhead and a power consumption of a pipelined analog-to-digital converter. Each stage of the pipelined analog-to-digital converter according to the disclosure comprises an analogue-to-digital converter, a digital-to-analog converter, a subtractor and an amplifier. According to the disclosure, an amplification time of the pipelined ADC is used for extra quantization, and a number of bits of each ADC is reduced on the premise of not increasing a number of stages of the pipelined ADC, so that a scale of each circuit is greatly reduced, and the power consumption and the area overhead are reduced.


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