The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 21, 2021

Filed:

Sep. 18, 2018
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Hassan Naser, Austin, TX (US);

Daniel Stasiak, Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/528 (2006.01); H01L 23/535 (2006.01); H01L 23/522 (2006.01); H01L 23/367 (2006.01); H01L 23/00 (2006.01); H01L 23/495 (2006.01);
U.S. Cl.
CPC ...
H01L 23/535 (2013.01); H01L 23/367 (2013.01); H01L 23/481 (2013.01); H01L 23/5226 (2013.01); H01L 23/5286 (2013.01); H01L 24/73 (2013.01); H01L 23/3677 (2013.01); H01L 23/49582 (2013.01); H01L 2224/73257 (2013.01);
Abstract

An integrated circuit module, system and method of providing power and signals is disclosed that includes a silicon chip and a package substrate having voltage connections and signal connections. The silicon chip includes a silicon substrate having a top surface, a bottom surface and circuitry formed therein, one or more front-side metal layers formed on the top surface of the silicon substrate, one or more back-side metal layers formed on the bottom surface of the silicon substrate, and one or more through silicon vias (TSVs) formed through the silicon substrate for creating a conductive pathway from the back-side of the silicon substrate to the front-side of the silicon substrate, preferably closest to the silicon substrate.


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