The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 21, 2021

Filed:

Jan. 09, 2020
Applicant:

Nanya Technology Corporation, New Taipei, TW;

Inventors:

Chiang-Lin Shih, New Taipei, TW;

Hsih-Yang Chiu, Taoyuan, TW;

Ching-Hung Chang, Taoyuan, TW;

Pei-Jhen Wu, Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/48 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); H01L 21/76804 (2013.01); H01L 21/76877 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01);
Abstract

A semiconductor structure and a method of manufacturing thereof are provided. The semiconductor includes a semiconductor integrated circuit device and a redistribution layer structure. The semiconductor integrated circuit device has a top surface and an electrode on the top surface. The redistribution layer structure is formed on the top surface. The redistribution layer structure includes an oxide layer, a nitride layer, a dielectric layer, a groove and a through via. The oxide layer and the nitride layer are formed on the top surface. The dielectric layer is formed on the nitride layer. The groove is formed at a topside of the dielectric layer and overlaps the electrode. The through via is formed at a bottom of the groove and extends within the electrode through the dielectric layer, the nitride layer and the oxide layer. The through via and the groove are filled with a conductive material.


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