The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 21, 2021

Filed:

Jul. 23, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Seong-Yul Park, Hwaseong-si, KR;

Myoung-Ho Kang, Suwon-si, KR;

Hyungkwan Park, Yongin-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/45 (2006.01); H01L 29/786 (2006.01); H01L 21/02 (2006.01); H01L 21/285 (2006.01); H01L 21/306 (2006.01); H01L 21/308 (2006.01); H01L 29/66 (2006.01); G06F 30/392 (2020.01); G03F 1/36 (2012.01);
U.S. Cl.
CPC ...
H01L 21/823807 (2013.01); G03F 1/36 (2013.01); G06F 30/392 (2020.01); H01L 21/02532 (2013.01); H01L 21/02603 (2013.01); H01L 21/28518 (2013.01); H01L 21/308 (2013.01); H01L 21/30604 (2013.01); H01L 21/823814 (2013.01); H01L 21/823871 (2013.01); H01L 27/092 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/45 (2013.01); H01L 29/66545 (2013.01); H01L 29/66742 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01);
Abstract

A method of fabricating a semiconductor device includes: (i) placing, on a first layout, first patterns that extend parallel to each other in a first direction and are spaced apart from each other in a second direction intersecting the first direction, (ii) extracting a low-density region on the first layout, (iii) defining an enclosure region that surrounds the first patterns, (iv) placing dot patterns on a second layout, (v) extracting, from the dot patterns, first dot patterns that overlap the low-density region and do not overlap the enclosure region, (vi) placing the extracted first dot patterns on the first layout, (vii) allowing the first dot patterns to extend in the first direction to form second patterns, and (viii) using the first and second patterns to respectively form first and second active patterns on a substrate.


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