The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 21, 2021
Filed:
Jun. 30, 2020
Applicant:
SK Hynix Inc., Icheon-si, KR;
Inventor:
Hee Joo Lee, Icheon-si, KR;
Assignee:
SK hynix Inc., Icheon-si, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/08 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01); G11C 16/30 (2006.01); G11C 16/20 (2006.01); G11C 16/04 (2006.01); G11C 16/32 (2006.01); G11C 11/56 (2006.01);
U.S. Cl.
CPC ...
G11C 16/20 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/30 (2013.01); G11C 16/32 (2013.01); G11C 16/3459 (2013.01); G11C 11/5621 (2013.01); G11C 11/5671 (2013.01);
Abstract
A memory device includes drain select lines, source select lines, a plurality of word lines arranged between the drain select lines and the source select lines, and a peripheral circuit configured to perform a program operation on selected memory cells connected to a selected word line among the plurality of word lines. The peripheral circuit includes a voltage generator configured to generate a voltage for initializing a channel of a plurality of memory cells respectively connected to the plurality of word lines in a program phase among a plurality of phases included in the program operation.