The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 21, 2021

Filed:

Apr. 12, 2018
Applicant:

Microsoft Technology Licensing, Llc, Redmond, WA (US);

Inventors:

Amol Ashok Ambardekar, Redmond, WA (US);

Chad Balling McBRIDE, North Bend, WA (US);

George Petre, Redmond, WA (US);

Larry Marvin Wall, Seattle, WA (US);

Kent D. Cedola, Bellevue, WA (US);

Boris Bobrov, Kirkland, WA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/02 (2006.01); G06N 3/063 (2006.01); G06N 3/04 (2006.01); G06F 12/0862 (2016.01); G06F 9/46 (2006.01); G06F 1/324 (2019.01); G06F 3/06 (2006.01); G06F 9/38 (2018.01); G06F 12/08 (2016.01); G06F 12/10 (2016.01); G06F 15/80 (2006.01); G06F 17/15 (2006.01); G06N 3/06 (2006.01); G06N 3/08 (2006.01); G06N 3/10 (2006.01); H03M 7/30 (2006.01); H04L 12/715 (2013.01); H04L 29/08 (2006.01); G06F 9/30 (2018.01); G06F 13/16 (2006.01); G06F 1/3234 (2019.01); G06F 12/02 (2006.01); G06F 13/28 (2006.01); H03M 7/46 (2006.01); H04L 12/723 (2013.01);
U.S. Cl.
CPC ...
G06N 3/063 (2013.01); G06F 1/324 (2013.01); G06F 1/3275 (2013.01); G06F 3/0604 (2013.01); G06F 3/067 (2013.01); G06F 3/0631 (2013.01); G06F 9/30087 (2013.01); G06F 9/3836 (2013.01); G06F 9/3887 (2013.01); G06F 9/46 (2013.01); G06F 12/0207 (2013.01); G06F 12/08 (2013.01); G06F 12/0862 (2013.01); G06F 12/10 (2013.01); G06F 13/1673 (2013.01); G06F 13/1689 (2013.01); G06F 13/28 (2013.01); G06F 15/8007 (2013.01); G06F 17/15 (2013.01); G06N 3/04 (2013.01); G06N 3/049 (2013.01); G06N 3/0454 (2013.01); G06N 3/06 (2013.01); G06N 3/0635 (2013.01); G06N 3/08 (2013.01); G06N 3/10 (2013.01); H03M 7/6005 (2013.01); H03M 7/6011 (2013.01); H03M 7/70 (2013.01); H04L 45/04 (2013.01); H04L 67/02 (2013.01); H04L 67/1002 (2013.01); G06F 2209/484 (2013.01); G06F 2209/485 (2013.01); G06F 2212/657 (2013.01); H03M 7/46 (2013.01); H04L 45/50 (2013.01); Y02D 10/00 (2018.01);
Abstract

A deep neural network (DNN) module utilizes parallel kernel and parallel input processing to decrease bandwidth utilization, reduce power consumption, improve neuron multiplier stability, and provide other technical benefits. Parallel kernel processing enables the DNN module to load input data only once for processing by multiple kernels. Parallel input processing enables the DNN module to load kernel data only once for processing with multiple input data. The DNN module can implement other power-saving techniques like clock-gating (i.e. removing the clock from) and power-gating (i.e. removing the power from) banks of accumulators based upon usage of the accumulators. For example, individual banks of accumulators can be power-gated when all accumulators in a bank are not in use, and do not store data for a future calculation. Banks of accumulators can also be clock-gated when all accumulators in a bank are not in use, but store data for a future calculation.


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