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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11205035 B1

PDFFull Text
Date of Patent:
Dec. 21, 2021

Filed:

Jun. 23, 2020

Bump connection placement in quantum devices in a flip chip configuration

Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Dongbing Shao, Wappingers Falls, NY (US);

Markus Brink, White Plains, NY (US);

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);

Attorneys:

Garg Law Firm, PLLC

Rakesh Garg

Douglas Pearson

Primary Examiner:

Leigh M Garbowski

Int. Cl.
CPC ...
G06F 30/30 (2020.01); H01L 23/00 (2006.01); G06F 30/398 (2020.01); G06F 30/39 (2020.01); G06F 30/392 (2020.01); G06F 30/337 (2020.01); G06F 30/327 (2020.01); G06F 111/12 (2020.01); G06F 111/14 (2020.01); G06F 30/394 (2020.01); G06F 30/3308 (2020.01); B82Y 10/00 (2011.01); G06N 10/00 (2019.01); G06F 113/18 (2020.01); G06F 115/12 (2020.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
G06F 30/398 (2020.01); G06F 30/39 (2020.01); G06F 30/392 (2020.01); H01L 24/10 (2013.01); B82Y 10/00 (2013.01); G06F 30/30 (2020.01); G06F 30/327 (2020.01); G06F 30/337 (2020.01); G06F 30/3308 (2020.01); G06F 30/394 (2020.01); G06F 2111/12 (2020.01); G06F 2111/14 (2020.01); G06F 2113/18 (2020.01); G06F 2115/12 (2020.01); G06N 10/00 (2019.01); H01L 23/49811 (2013.01); H01L 23/49838 (2013.01); H01L 24/06 (2013.01); H01L 24/14 (2013.01); H01L 2225/06513 (2013.01); Y10S 977/72 (2013.01); Y10S 977/839 (2013.01);
Abstract

Within a layout of a first surface in a flip chip configuration, a bump restriction area is mapped according to a set of bump placement restrictions, wherein a first bump placement restriction specifies an allowed distance range between a bump and a qubit chip element in a layout of the first surface in the flip chip configuration. An electrically conductive material is deposited outside the bump restriction area, to form the bump, wherein the bump comprises an electrically conductive structure that electrically couples a signal from the first surface and is positioned according to the set of bump placement restrictions.

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