The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 21, 2021

Filed:

Sep. 18, 2019
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventor:

Yasuo Sasaki, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/312 (2018.01); G06F 9/46 (2006.01); G06F 12/08 (2016.01); G06F 9/34 (2018.01); G06F 9/48 (2006.01); G06F 9/30 (2018.01); G06F 12/0831 (2016.01);
U.S. Cl.
CPC ...
G06F 9/4881 (2013.01); G06F 9/30101 (2013.01); G06F 9/30145 (2013.01); G06F 9/30043 (2013.01); G06F 12/0835 (2013.01); G06F 2213/2806 (2013.01);
Abstract

A semiconductor device capable of suppressing performance degradation and systems using the same are provided. The semiconductor device includes a plurality of processors CPUand CPU, a scheduling device(ID) connected to the processors CPUand CPUfor controlling the processors CPUand CPUto execute a plurality of tasks in real time, memoriesandaccessed by the processors CPUand CPUto store data by executing the tasks, and access monitor circuitsfor monitoring accesses to the memories by the processors CPUand CPU. When an access to the memory is detected by the access monitor circuit, the data stored in the memoryis transferred based on the destination information of the data stored in the memory


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