The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 21, 2021

Filed:

Oct. 17, 2017
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Jindrich Zejda, Saratoga, CA (US);

Elliott Delaye, San Jose, CA (US);

Yongjun Wu, Cupertino, CA (US);

Aaron Ng, San Jose, CA (US);

Ashish Sirasao, San Jose, CA (US);

Khang K. Dao, San Jose, CA (US);

Christopher J. Case, San Jose, CA (US);

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/45 (2006.01); G06F 8/41 (2018.01); G06N 3/02 (2006.01); G06F 13/28 (2006.01); G06F 8/30 (2018.01); G06F 9/451 (2018.01); G06F 9/50 (2006.01); G06F 13/362 (2006.01);
U.S. Cl.
CPC ...
G06F 8/47 (2013.01); G06F 8/315 (2013.01); G06F 8/447 (2013.01); G06F 9/451 (2018.02); G06F 9/5038 (2013.01); G06F 13/28 (2013.01); G06N 3/02 (2013.01); G06F 13/362 (2013.01);
Abstract

Embodiments herein describe techniques for interfacing a neural network application with a neural network accelerator that operate on two heterogeneous computing systems. For example, the neural network application may execute on a central processing unit (CPU) in a computing system while the neural network accelerator executes on a FPGA. As a result, when moving a software-hardware boundary between the two heterogeneous systems, changes may be made to both the neural network application (using software code) and to the accelerator (using RTL). The embodiments herein describe a software defined approach where shared interface code is used to express both sides of the interface between the two heterogeneous systems in a single abstraction (e.g., a software class).


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