The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 21, 2021
Filed:
Jun. 03, 2020
Arm Limited, Cambridge, GB;
Nicholas Andrew Pfister, Austin, TX (US);
Arm Limited, Cambridge, GB;
Abstract
An apparatus and method are provided for performing bit permutation operations. The apparatus has an interface for receiving an input data operand and a control operand. The input data operand comprises one or more data elements, each data element comprising a plurality of bits, and the control operand provides control information identifying bit permutations required when performing a given bit permutation operation on each data element. The bit permute circuitry treats the input data operand as a plurality of fixed size data portions, each data element comprising one or more of the data portions with the number being dependent on the data element size. The bit permute circuitry performs bit permutation operations on each data portion of the input data operand, using the control information provided for that data portion, generating, for each data portion, at least one intermediate result. Result generation circuitry generates, from the intermediate results, a final result operand comprising one or more result elements, each result element providing the result of performing the given bit permutation operation on the corresponding data element of the input data operand. The result generation circuitry comprises a multi-level network of shifter circuits, shifter circuits at a first level performing shift operations using as inputs at least a subset of the intermediate results, and shifter circuits at each subsequent level performing shift operations using inputs derived from the outputs of the shifter circuits at a preceding level of the network. Control circuitry analyses the control information provided by the control operand in order to generate control signals that control the shift operations performed by the shifter circuits.