The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 14, 2021

Filed:

Oct. 27, 2020
Applicant:

Empower Semiconductor, Fremont, CA (US);

Inventor:

Parag Oak, Sunnyvale, CA (US);

Assignee:

EMPOWER SEMICONDUCTOR, INC., Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 17/082 (2006.01); H03K 5/24 (2006.01);
U.S. Cl.
CPC ...
H03K 17/0822 (2013.01); H03K 5/24 (2013.01);
Abstract

A voltage tolerant interface circuit includes an input terminal and one or more low-voltage transistors for generating an output from the voltage tolerant interface circuit based on a voltage received at the input terminal. The voltage tolerant interface circuit also includes a blocking transistor coupled between a control terminal of at least one low-voltage transistor and the input terminal. In some implementations, the blocking transistor is configured to protect the control terminal of the low-voltage transistor by blocking the voltage received at the input terminal when the voltage exceeds a voltage tolerance of the low-voltage transistor. In other implementations, the low-voltage transistor receives a supply voltage higher than the voltage tolerance of the low-voltage transistor. In that implementation, the blocking transistor is configured to protect the control terminal of the low-voltage transistor by blocking the voltage received at the input terminal when the voltage is below a predetermined threshold.


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