The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 14, 2021

Filed:

Dec. 17, 2020
Applicant:

Seiko Epson Corporation, Toyko, JP;

Inventors:

Hideo Haneda, Matsumoto, JP;

Yasuhiro Sudo, Chino, JP;

Akio Tsutsumi, Chino, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03B 5/36 (2006.01); G06F 1/08 (2006.01); G04F 10/00 (2006.01); H03B 5/04 (2006.01); G06F 1/04 (2006.01);
U.S. Cl.
CPC ...
H03B 5/36 (2013.01); G04F 10/005 (2013.01); G06F 1/04 (2013.01); G06F 1/08 (2013.01); H03B 5/04 (2013.01);
Abstract

An oscillator includes a resonator, a clock signal generation circuit, a clock signal output terminal, an external signal input terminal, an interface circuit, and an interface terminal. The clock signal generation circuit oscillates the resonator to generate a clock signal. The clock signal output terminal outputs the clock signal. An external signal is input to the external signal input terminal. The interface circuit outputs time difference information obtained by measuring a time difference between a transition timing of a first signal based on the external signal input from the external signal input terminal and a transition timing of a second signal based on the clock signal, or frequency information obtained by measuring a frequency of a first clock signal, which is one of the clock signal and the external clock signal, based on a frequency of a second clock signal, which is the other of the clock signal and the external clock signal. The interface terminal is coupled to the interface circuit.


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