IDiyas

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11201212 B1

PDFFull Text
Date of Patent:
Dec. 14, 2021

Filed:

Aug. 17, 2018

Mosfet with ultra low drain leakage

Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Joel P. de Souza, Putnam Valley, NY (US);

Keith E. Fogel, Hopewell Junction, NY (US);

Jeehwan Kim, Cambridge, MA (US);

Devendra K. Sadana, Pleasantville, NY (US);

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);

Attorneys:

Tutunjian & Bitetto, P.C.

Erik Johnson

Primary Examiner:

Erik T K. Peterson

Int. Cl.
CPC ...
H01L 29/08 (2006.01); H01L 29/06 (2006.01); H01L 29/786 (2006.01); H01L 21/02 (2006.01); H01L 29/267 (2006.01); H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 29/22 (2006.01); H01L 29/24 (2006.01); H01L 29/78 (2006.01); H01L 29/423 (2006.01); H01L 23/31 (2006.01); H01L 23/29 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0847 (2013.01); H01L 21/02554 (2013.01); H01L 21/02565 (2013.01); H01L 21/28264 (2013.01); H01L 23/3171 (2013.01); H01L 29/0603 (2013.01); H01L 29/0638 (2013.01); H01L 29/0653 (2013.01); H01L 29/22 (2013.01); H01L 29/247 (2013.01); H01L 29/267 (2013.01); H01L 29/66636 (2013.01); H01L 29/78 (2013.01); H01L 29/78603 (2013.01); H01L 21/02576 (2013.01); H01L 21/28114 (2013.01); H01L 23/291 (2013.01); H01L 29/42376 (2013.01); H01L 29/66727 (2013.01);
Abstract

A semiconductor device includes a monocrystalline substrate configured to form a channel region between two recesses in the substrate. A gate conductor is formed on a passivation layer over the channel region. Dielectric pads are formed in a bottom of the recesses and configured to prevent leakage to the substrate. Source and drain regions are formed in the recesses on the dielectric pads from a deposited non-crystalline n-type material with the source and drain regions making contact with the channel region.

Find Patent Forward Citations

Loading…