The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 14, 2021

Filed:

Jan. 19, 2018
Applicant:

Siemens Aktiengesellschaft, Munich, DE;

Inventor:

Bernd Kürten, Obermichelbach, DE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/373 (2006.01); H01L 23/40 (2006.01); H01L 23/492 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3735 (2013.01); H01L 23/4006 (2013.01); H01L 23/492 (2013.01); H01L 24/32 (2013.01); H01L 24/83 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/8384 (2013.01); H01L 2224/83801 (2013.01); H01L 2924/3511 (2013.01);
Abstract

A structured metal layer in contact with an electronic component is applied on an upper side of a substrate of electrically insulating material. A metallic contact layer is applied to an underside of the substrate, with the underside configured as planar surface in a state of the substrate that is free of mechanical stress. The contact layer is connected to a metallic base plate via an intermediate layer. The contact layer is connected to the metallic base plate at an elevated temperature. The semiconductor module is then cooled. The side of the metallic base plate facing the substrate and the side of the metallic base plate facing away from the substrate are configured as planar surfaces in a state of the base plate that is free of mechanical stress. Upon cooling of the semiconductor module, the base plate forms a concave curvature on its side facing away from the substrate.


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