The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 14, 2021

Filed:

Jan. 30, 2020
Applicant:

Emc Ip Holding Company Llc, Hopkinton, MA (US);

Inventors:

Jack Fu, Brighton, MA (US);

Jaeyoo Jung, Shrewsbury, MA (US);

Arieh Don, Newton, MA (US);

Assignee:

EMC IP Holding Company LLC, Hopkinton, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 12/084 (2016.01); G06F 12/0862 (2016.01);
U.S. Cl.
CPC ...
G06F 12/084 (2013.01); G06F 12/0862 (2013.01); G06F 2212/602 (2013.01); G06F 2212/604 (2013.01); G06F 2212/621 (2013.01);
Abstract

A processing node of a storage system may determine that a host system is implementing a cache-slot aware, round-robin IO distribution algorithm (CA-RR). The processing node may be configured to determine when a sufficient number of sequential IOs will be received to consume a cache slot of the a processing node. If the processing node knows that the host system is implementing CA-RR, then, in response to determining the sufficient number, the processing node may send a communication informing the next processing node about the sequential cache slot hit. If the sequential IO operation(s) are read operation(s), the next processing node may prefetch at least a cache-slot worth of next consecutive data portions. If the sequential IO operation(s) are write operation(s), then the next processing node may request allocation of one or more local cache slots for the forthcoming sequential write operations.


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