The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 14, 2021

Filed:

Mar. 26, 2021
Applicant:

Sambanova Systems, Inc., Palo Alto, CA (US);

Inventors:

Raghunath Shenbagam, San Jose, CA (US);

Ravinder Kumar, Fremont, CA (US);

Assignee:

SambaNova Systems, Inc., Palo Alto, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/50 (2006.01); G06F 9/445 (2018.01); H04L 12/841 (2013.01); G06F 9/455 (2018.01); G06F 15/78 (2006.01); H04L 12/24 (2006.01);
U.S. Cl.
CPC ...
G06F 9/5077 (2013.01); G06F 9/44505 (2013.01); G06F 9/45558 (2013.01); G06F 9/5044 (2013.01); G06F 15/7892 (2013.01); H04L 47/28 (2013.01); G06F 2009/4557 (2013.01); G06F 2009/45595 (2013.01); G06F 2209/5011 (2013.01); G06F 2213/0062 (2013.01); G06F 2213/0064 (2013.01); H04L 41/0896 (2013.01);
Abstract

A system is described that has a node and runtime logic. The node has a plurality of processing elements operatively coupled by interconnects. The runtime logic is configured to receive target interconnect bandwidth, target interconnect latency, rated interconnect bandwidth and rated interconnect latency. The runtime logic responds by allocating to configuration files defined by the application graph: (1) processing elements in the plurality of processing elements, and (2) interconnects between the processing elements. The runtime logic further responds by executing the configuration files using the allocated processing elements and the allocated interconnects.


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