The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 07, 2021
Filed:
Apr. 17, 2018
Applicant:
Cirrus Logic International Semiconductor Ltd., Edinburgh, GB;
Inventor:
Marek Sebastian Piechocinski, Edinburgh, GB;
Assignee:
Cirrus Logic, Inc., Austin, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04R 19/04 (2006.01); H04R 1/08 (2006.01); B01D 46/10 (2006.01); B81B 7/00 (2006.01); B81C 1/00 (2006.01); H04R 19/00 (2006.01);
U.S. Cl.
CPC ...
H04R 19/04 (2013.01); B01D 46/10 (2013.01); B81B 7/0058 (2013.01); B81B 7/0064 (2013.01); B81C 1/00333 (2013.01); H04R 1/086 (2013.01); H04R 19/005 (2013.01); B01D 2279/45 (2013.01); B81B 2201/0257 (2013.01); B81B 2203/0127 (2013.01); B81B 2203/0315 (2013.01); B81B 2207/012 (2013.01); B81C 2201/0105 (2013.01); B81C 2201/0132 (2013.01); H04R 2201/003 (2013.01);
Abstract
MEMS devices comprise a filter configured and arranged to inhibit the entry of particles into at least a region of the interior of the substrate cavity from a region underlying the substrate.