The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 07, 2021

Filed:

Jan. 22, 2021
Applicant:

Ciena Corporation, Hanover, MD (US);

Inventors:

Soheyl Ziabakhsh Shalmani, Kanata, CA;

Hazem Beshara, Ottawa, CA;

Mohammad Honarparvar, Gatineau, CA;

Sadok Aouini, Gatineau, CA;

Christopher Kurowski, Nepean, CA;

Naim Ben-Hamida, Nepean, CA;

Assignee:

Ciena Corporation, Hanover, MD (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/10 (2006.01); H03M 1/12 (2006.01); G06F 1/08 (2006.01); H03M 1/06 (2006.01); H03M 1/00 (2006.01);
U.S. Cl.
CPC ...
H03M 1/124 (2013.01); G06F 1/08 (2013.01); H03M 1/1009 (2013.01); H03M 1/001 (2013.01); H03M 1/06 (2013.01); H03M 1/10 (2013.01); H03M 1/12 (2013.01);
Abstract

Described are apparatus and methods for analog to digital converter (ADC) with factoring and background clock calibration. An apparatus includes an ADC configured to sample and convert differential input signals using a reference clock to obtain a defined number of samples during a first state in an acquisition clock cycle, and a finite state machine circuit configured to obtain the defined number of samples from the ADC using a clock based on the reference clock, factor the defined number of samples based on at least a common mode offset associated with the ADC, and send offset factored output to a controller.


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