The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 07, 2021

Filed:

Sep. 08, 2020
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Pangjie Xu, San Jose, CA (US);

Jelam K. Parekh, Milpitas, CA (US);

Mohamed H. Abu-Rahma, Mountain View, CA (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/06 (2006.01); G04F 10/00 (2006.01); H03M 7/16 (2006.01);
U.S. Cl.
CPC ...
H03M 1/0629 (2013.01); G04F 10/005 (2013.01); H03M 7/165 (2013.01);
Abstract

Systems, apparatuses, and methods for implementing an anti-aliasing technique for a time-to-digital converter are described. A pulse generator generates a pulse with a width that is representative of a voltage level of a supply voltage. A buffer chain receives the pulse from the pulse generator. A first sum is calculated by adding together a number of one bits in a first portion of the buffer chain. Also, a second sum is calculated by adding together a number of one bits in a second portion of the buffer chain. Then, a third sum is calculated by adding the first sum to the second sum if the first sum is saturated. Otherwise, the third sum is equal to the first sum if the first sum is not saturated. The third sum is used as a representation of the voltage level of the supply voltage.


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