The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 07, 2021
Filed:
Apr. 07, 2020
Xilinx, Inc., San Jose, CA (US);
Samudyatha Suryanarayana, Sunnyvale, CA (US);
Vinit Shah, Los Gatos, CA (US);
David S. Smith, Redwood City, CA (US);
Andrew Tabalujan, Milpitas, CA (US);
Arvind R. Bomdica, Palo Alto, CA (US);
XILINX, INC., San Jose, CA (US);
Abstract
Apparatus and associated methods relate to an I/O bank impedance calibration circuit having (a) a replica master resistor coupled to an external precision resistor, and (b) a control circuit configured to calibrate an output impedance of the master resistor to generate a calibrated code to control a replica slave resistor in each bank. In an illustrative example, a signal applied to the replica master resistor may be compared against a programmable reference signal. The control circuit may generate the calibrated code, in response to the comparison result, to calibrate the output impedance of the replica master resistor. By implementing the replica master resistor and the replica slave resistor, impedances of a large number of IOs or banks may be calibrated by the impedance calibration circuit using a single one reference pin.