The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 07, 2021

Filed:

Jun. 14, 2019
Applicant:

Melexis Technologies NV, Tessenderlo, BE;

Inventor:
Assignee:

MELEXIS TECHNOLOGIES NV, Tessenderlo, BE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/84 (2006.01); H01L 23/31 (2006.01); H01L 21/02 (2006.01); H01L 21/768 (2006.01); H01L 23/29 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 23/00 (2006.01); H01L 29/40 (2006.01); H01L 37/02 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3171 (2013.01); H01L 21/02274 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 23/291 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/53257 (2013.01); H01L 23/53271 (2013.01); H01L 24/05 (2013.01); H01L 29/402 (2013.01); H01L 29/84 (2013.01); H01L 37/02 (2013.01); H01L 2224/05025 (2013.01);
Abstract

A semiconductor device comprises a first doped semiconductor layer, a second doped semiconductor layer, an oxide layer covering the first doped semiconductor layer and the second doped semiconductor layer, and an interconnect. The first doped semiconductor layer is electrically connected with the second doped semiconductor layer by means of the interconnect which crosses over a sidewall of the second doped semiconductor layer. The interconnect comprises a metal filled slit in the oxide layer. At least one electronic component is formed in the first and/or second semiconductor layer. The semiconductor device moreover comprises a passivation layer which covers the first and second doped semiconductor layers and the oxide layer.


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