The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 07, 2021

Filed:

Apr. 16, 2020
Applicants:

Ordos Yuansheng Optoelectronics Co., Ltd., Inner Mongolia, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Lei Li, Beijing, CN;

Jun Fan, Beijing, CN;

Le Ta, Beijing, CN;

Yusheng Liu, Beijing, CN;

Yongqiang Zhang, Beijing, CN;

Mei Li, Beijing, CN;

Yafei Li, Beijing, CN;

Peng Liu, Beijing, CN;

Zhixuan Guo, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/36 (2006.01); H01L 27/12 (2006.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01);
U.S. Cl.
CPC ...
G09G 3/3607 (2013.01); G09G 3/3648 (2013.01); G09G 3/3685 (2013.01); H01L 27/124 (2013.01); G02F 1/1368 (2013.01); G02F 1/136286 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0443 (2013.01);
Abstract

The present disclosure provides a display panel, a method of driving the display panel and a display device. Each signal input sub-circuitry of the display panel includes at least two transistors. A same control signal is applied to control signal lines corresponding to a same signal input sub-circuitry, different control signals are applied to control signal lines corresponding to different signal input sub-circuitries, and time periods within which the different control signals are at active levels are staggered from each other. A sum of width-to-length ratios of channels of the at least two transistors is equal to a first predetermined value, and an overlapping area of the gate electrode of each of the at least two transistors relative to an active layer of the transistor is smaller than a second predetermined value in a direction perpendicular to a base substrate of the display panel.


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