The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 07, 2021

Filed:

Dec. 09, 2019
Applicant:

Samsung Display Co., Ltd., Yongin-si, KR;

Inventors:

Chul Kyu Kang, Yongin-si, KR;

Sung Hwan Kim, Yongin-si, KR;

Soo Hee Oh, Yongin-si, KR;

Dong Sun Lee, Yongin-si, KR;

Sang Moo Choi, Yongin-si, KR;

Assignee:

Samsung Display Co., Ltd., Yongin-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/30 (2006.01); G09G 3/36 (2006.01); G09G 3/3266 (2016.01); G09G 3/3291 (2016.01); G09G 3/3233 (2016.01);
U.S. Cl.
CPC ...
G09G 3/3266 (2013.01); G09G 3/3233 (2013.01); G09G 3/3291 (2013.01); G09G 2310/0202 (2013.01); G09G 2310/0278 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01);
Abstract

A stage of a scan driver for a display device, the stage includes: an output unit to output to an output terminal either a signal supplied to a first clock terminal corresponding to voltage of a first driving node or a voltage of a second power source corresponding to voltage of a second driving node; an input unit to control the voltage of the first driving node corresponding to signals supplied to a first input terminal, and the input unit to control the voltage of the second driving node corresponding to signals supplied to a second input terminal and a second clock terminal; a first signal processor including a second capacitor coupled between the second driving node and a second node, the first signal processor to control the voltage of the second driving node corresponding to signals supplied to a third clock terminal and a fourth clock terminal, the first signal processor to control a potential difference between both ends of the second capacitor corresponding to the signal supplied to the fourth clock terminal; and a second signal processor to control the voltage of the first driving node corresponding to the signal supplied to the first clock terminal.


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