The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 07, 2021
Filed:
Aug. 11, 2020
Applicant:
Texas Instruments Incorporated, Dallas, TX (US);
Inventors:
Assignee:
TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/3312 (2020.01); G06F 30/30 (2020.01); G06F 30/398 (2020.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); G01R 31/28 (2006.01); G01R 27/28 (2006.01); G01R 31/36 (2020.01); H03K 19/00 (2006.01); H01L 29/10 (2006.01); H01L 25/00 (2006.01); G06G 7/62 (2006.01); H01L 23/58 (2006.01);
U.S. Cl.
CPC ...
G06F 30/3312 (2020.01); G06F 30/30 (2020.01); G06F 30/398 (2020.01); G01R 27/28 (2013.01); G01R 31/28 (2013.01); G01R 31/36 (2013.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); G06G 7/62 (2013.01); H01L 23/58 (2013.01); H01L 25/00 (2013.01); H01L 29/10 (2013.01); H03K 19/00 (2013.01);
Abstract
A method that includes disabling circuit paths in a circuit under test during transition fault testing (TFT) of valid timing paths of the circuit under test. The method then tests the circuit paths at slower clock speeds than the clock speed of the valid timing paths during TFT of the circuit paths. Finally, the method tests the circuit paths and the valid timing paths to facilitate testing of the circuit under test.