The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 07, 2021

Filed:

May. 11, 2020
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Hillel Mendelson, Kibbutz Hahotrim, IL;

Tom Kolan, Haifa, IL;

Vitali Sokhin, Haifa, IL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/263 (2006.01); G06F 11/36 (2006.01); G06F 9/302 (2018.01); G06F 12/0808 (2016.01); G06F 9/30 (2018.01); G06F 9/54 (2006.01); G06F 12/0882 (2016.01); G06F 9/38 (2018.01); G06F 11/22 (2006.01);
U.S. Cl.
CPC ...
G06F 11/3692 (2013.01); G06F 9/30043 (2013.01); G06F 9/30101 (2013.01); G06F 9/544 (2013.01); G06F 11/3684 (2013.01); G06F 11/3688 (2013.01); G06F 12/0808 (2013.01); G06F 12/0882 (2013.01); G06F 9/3808 (2013.01); G06F 9/3812 (2013.01); G06F 11/2236 (2013.01); G06F 11/263 (2013.01); G06F 11/3648 (2013.01);
Abstract

Method, apparatus and product for automatically introducing register dependency into tests. A test template represents an abstract test scenario to be utilized for testing a target processor. The abstract test scenario requires that a value be assigned to a register. A test that implements the abstract test scenario is generated. The test is a set of instructions that are executable by the target processor. The generation of the test comprises: determining a memory address to retain the value in a memory that is accessible to the target processor; and adding to the test an instruction to load to the register the value from the memory address, whereby adding a register dependency to the test that is not required by the abstract test scenario. The test can be executed on the target processor or simulation thereof.


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